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The IEEE 1149.1 (JTAG) offers a standard for Test Access Port (TAP) and boundary scan architecture for testing digital ICs. This widely accepted standard is applicable to all digital IC designs ranging from components to complex SoCs. The JTAG eVC is a complete verification environment based on the IEEE 1149.1-2001 (JTAG) standard. From developing a JTAG TAP controller to designing a complete chip-level test architecture, the JTAG eVC is a valuable tool for identifying design bugs, emphasizing protocol compatibility issues and ensuring smooth interoperability of testability features.
The figure above illustrates how an eVC Agent can be used to verify a typical IC with JTAG support. All shift chains are automatically verified through the standard TAP. Furthermore, all boundary scan cells are exercised and checked for appropriate Capture, Update and Scan behavior. Combine this eVC with the new IEEE 1500 Standard for Embedded Core Test (SECT) eVC for a complete System-on-Chip testability infrastructure verification solution. |
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