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IP/SOC 2005 (IP Based SoC Design) will be the 14th edition of the Working conference on hot topics in the design world, focusing for the past 5 years on IP based SoC design and hold in the well known Silicon and Alliance Nanometer Valley in the French Alps. This year, Globetech Solutions will be having a strong presence in the conference with two technical presentations in cutting edge verification topics. The topics are targetting advanced SoC, IP-based design, and are reflective of our commitment to innovation and investment on industrial R&D. Topic 1 | Track: | Industrial Verification and Methodology | | When: | December 8th, 13:30 | | Title: | "A Unified DFT Verification Methodology" by Stylianos Diamantidis, Iraklis Diamantidis, Thanasis Oikonomou | | Abstract: | As modern ICs transistor counts continue their frenzied climb according to Moore's Law, test infrastructures, the collection of logic dedicated to testing the structural integrity of silicon, are also fast growing in both area and complexity. Although Design-for-Test, or DFT, is a concept that has been around for a long time, semiconductor companies today are experiencing unprecedented pressure for providing complex DFT features. This trend is largely attributed to the need for controllability and observability within highly integrated SoCs and is driven by the inevitabilities of test economics. In a nanometer design era where silicon debug can take up to 30% of project time and semiconductor test cost typically accounts for 30-50% of total fabrication cost, DFT is assuming a critical role in product definition, design and delivery. Conversely, incomplete or ineffective DFT support due to poor specification or loose design can quickly become the critical path to making market windows and delivering products within cost restrictions. Much the same as for the rich features that drive today's IP-based SoC designs, DFT is also in need of a new approach for verifying that test infrastructures will lie within intent, specification and interoperability parameters. This paper will introduce a Unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test. | Topic 2
| Track: | Industrial Verification and Methodology | | When: | December 8th, 16:00 | | Title: | "Designing a CE-ATA Verification Environment for SoC Applications" by Ioannis Mavroidis, Globetech Solutions
| | Abstract: | In this paper we will describe a verification environment developed for the emerging CE-ATA interface. The environment is written in e and is fully compatible with Cadence's Specman EliteTM. As such, it can be used as a Plug-n-Play verification component into any SoC that implements a CE-ATA bus. The user has full control over every verification aspect, including actively driving generated stimuli onto the bus, or passively monitoring the bus for protocol compliance checking, and coverage collection.
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For more information on these technical presentations and Globetech Solutions, please contact Ann Germany at +30 23 10 31 35 53.
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