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Q&A: Why The e Verification Language Is Alive And Well
(Fri, 19 Feb 2010 20:40:12)

TLM-Driven Design and Verification Solution
(Wed, 15 Jul 2009 07:56:11)

'Compact JTAG’ standard targets on-chip debug
(Fri, 05 Sep 2008 13:26:06)

IEEE Working Group Announces Updated 1647-2008 e Language Standard
(Thu, 29 May 2008 14:39:42)

New standards effort targets verification IP interoperability
(Mon, 28 Apr 2008 14:33:11)

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Functional Verification IP

	IEEE 1149.7™ VIP
	IEEE 1149.1 (JTAG) eVC
	IEEE 1500 (SECT) eVC

Functional Verification IP

	UART eVC
	CE-ATA eVC
	IrDA® eVC

Latest News

	2010-02-19 Q&A: Why The e Verification Language Is Alive And Well - Cadence.com
	2010-02-11 IPextreme and Globetech Solutions Announce Availability of Industry’s First Complete IEEE 1149.7 cJTAG IP Solution
	2009-07-15 TLM-Driven Design and Verification Solution - Cadence.com
	2008-09-05 'Compact JTAG’ standard targets on-chip debug - SCDsource

Customer Quotes

Globetech a premier Cadence partner
"Globetech is a [Cadence] premier Verification Alliance Partner with years of verification expertise, complemented by readily available verification IP. They substantially improve customers' time to productivity, and give them greater confidence in first-pass success."

Steven Glaser, Corporate VP Marketing, Cadence Verification Division [read more]