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[ Post-silicon | Papers ]
Presented at the 3rd IEEE Workshop on Infrastructure IP, Palm Spings, California, USA, this paper discusses a comprehensive approach to designing a DFT verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy.
[ Post-silicon | Papers ]
In this technical paper, we elaborate on the need to fully verify test infrastructures in modern SoCs and present a functional coverage-driven approach based on the IEEE 1500 eVC.
e Verification Components (eVCs)
Pre-verified, reusable, plug-n-play, verification environments based on the advanced e Hardware Verification Language (HVL).
[ eVCs | Papers ]
This article offers solutions to the challenges that arise in multiple interface crosschecking and presents useful practices for this type of eVC-based verification architecture. Furthermore, the discussion is supported by an example of a commercially available eVC which implements cross-checking between two distinct interfaces.

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Functional Verification IP
UART eVC
CE-ATA eVC
IrDA® eVC
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