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[ Post-silicon | Papers ]
This paper introduces a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.
Globetech Solutions adds CE-ATA to portfolio of Verification IP
(Wed, 30 Nov 2005 06:51:09)
SystemVerilog won't kill 'e', say proponents
(Tue, 22 Nov 2005 05:07:41)
[ Post-silicon | Papers ]
This brief article discusses how to plan DFT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical, and fully automated path from specification to closure.
[ Cadence VPA | Papers ]
Project management is all about planning and execution. But if everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes down to the adage, “Begin with the end in mind.” A good plan contains detailed goals using measurable metrics, along with optimal resource usage and realistic schedule estimates.

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IPextreme and Globetech Solutions Announce Availability of Industry’s First Complete IEEE 1149.7 cJTAG IP Solution
“Ease of integration and having a complete solution is critical to the success of any semiconductor IP core. Our close working relationship with Globetech, a leader in design verification and test solutions, will ensure that our customers will have interoperable world class VIP available for integration of our cJTAG SIP into their SoC.”

Rick Tomihiro, VP of Marketing, IPextreme [read more]