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[ Post-silicon | Papers ]
This brief article discusses how to plan DFT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical, and fully automated path from specification to closure.
[ Storage | Brochures ]
The CE-ATA eVC, based on a layered checker architecture, can be used to verify CE-ATA Hosts and Devices.
[ Cadence VPA | Papers ]
Project management is all about planning and execution. But if everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes down to the adage, “Begin with the end in mind.” A good plan contains detailed goals using measurable metrics, along with optimal resource usage and realistic schedule estimates.
[ Post-silicon | Papers ]
Presented at the 3rd IEEE Workshop on Infrastructure IP, Palm Spings, California, USA, this paper discusses a comprehensive approach to designing a DFT verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy.
[ Post-silicon | Papers ]
In this technical paper, we elaborate on the need to fully verify test infrastructures in modern SoCs and present a functional coverage-driven approach based on the IEEE 1500 eVC.

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IrDA® eVC
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