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[ Cadence VPA | Papers ]
In this article, publised in the Cadence Incisive Newsletter, we discuss the clear advantages Scenario Builder offers to the VIP ecosystem, as well as how VIP providers can leverage Scenario Builder to extend benefits to the end user.
[ Cadence VPA | Papers ]
Project management and automation are quickly becoming the most critical elements in the overall design and verification process. The most effective verification management strategy requires that design teams focus on some key features for success.
[ Storage | Papers ]

In this paper we describe a verification environment developed for the emerging CE-ATA interface that can be used as a plug-n-play verification component into any SoC that implements a CE-ATA bus. The paper was presented at IP/SoC 2005, Grenoble, France.
[ Post-silicon | Papers ]
This paper introduces a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.
Design For Testability (DFT) Consulting

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