Project management is all about planning and execution. But if everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes down to the adage, “Begin with the end in mind.” A good plan contains detailed goals using measurable metrics, along with optimal resource usage and realistic schedule estimates.

Presented at the 3rd IEEE Workshop on Infrastructure IP, Palm Spings, California, USA, this paper discusses a comprehensive approach to designing a DFT verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy.

In this technical paper, we elaborate on the need to fully verify test infrastructures in modern SoCs and present a functional coverage-driven approach based on the IEEE 1500 eVC.

This article offers solutions to the challenges that arise in multiple interface crosschecking and presents useful practices for this type of eVC-based verification architecture. Furthermore, the discussion is supported by an example of a commercially available eVC which implements cross-checking between two distinct interfaces.