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[ Cadence VPA ]
In this article, publised in the Cadence Incisive Newsletter, we discuss the clear advantages Scenario Builder offers to the VIP ecosystem, as well as how VIP providers can leverage Scenario Builder to extend benefits to the end user.
[ Cadence VPA ]
Project management and automation are quickly becoming the most critical elements in the overall design and verification process. The most effective verification management strategy requires that design teams focus on some key features for success.
[ Storage ]

In this paper we describe a verification environment developed for the emerging CE-ATA interface that can be used as a plug-n-play verification component into any SoC that implements a CE-ATA bus. The paper was presented at IP/SoC 2005, Grenoble, France.
[ Post-silicon ]
This paper introduces a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.
[ Post-silicon ]
This brief article discusses how to plan DFT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical, and fully automated path from specification to closure.

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IrDA® eVC
Customer Quotes
IPextreme and Globetech Solutions Announce Availability of Industry’s First Complete IEEE 1149.7 cJTAG IP Solution
“Ease of integration and having a complete solution is critical to the success of any semiconductor IP core. Our close working relationship with Globetech, a leader in design verification and test solutions, will ensure that our customers will have interoperable world class VIP available for integration of our cJTAG SIP into their SoC.”

Rick Tomihiro, VP of Marketing, IPextreme [read more]