Home > Resources > Papers
Home > Topics > Post-silicon
Any of these categories
This paper introduces a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.
This brief article discusses how to plan DFT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical, and fully automated path from specification to closure.
Presented at the 3rd IEEE Workshop on Infrastructure IP, Palm Spings, California, USA, this paper discusses a comprehensive approach to designing a DFT verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy.
In this technical paper, we elaborate on the need to fully verify test infrastructures in modern SoCs and present a functional coverage-driven approach based on the IEEE 1500 eVC.



Functional Verification IP
UART eVC
CE-ATA eVC
IrDA® eVC
Customer Quotes
Globetech a premier Cadence partner
"Globetech is a [Cadence] premier Verification Alliance Partner with years of verification expertise, complemented by readily available verification IP. They substantially improve customers' time to productivity, and give them greater confidence in first-pass success."

Steven Glaser, Corporate VP Marketing, Cadence Verification Division [read more]