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In this paper we describe a verification environment developed for the emerging CE-ATA interface that can be used as a plug-n-play verification component into any SoC that implements a CE-ATA bus. The paper was presented at IP/SoC 2005, Grenoble, France.
CE-ATA eVC
A complete verification environment capable of verifying both CE-ATA Host or Device designs based on a layered checker model.
[ Storage | Brochures ]
The CE-ATA eVC, based on a layered checker architecture, can be used to verify CE-ATA Hosts and Devices.
[ Post-silicon | Brochures ]
The JTAG eVC is a complete DFT verification environment capable of verifying IEEE 1149.1 test infrastructures.
[ Post-silicon | Brochures ]
The IEEE 1500 eVC is an DFT verification environment capable of verifying IEEE 1500 compliant test infrastructures.

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Functional Verification IP
UART eVC
CE-ATA eVC
IrDA® eVC
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François Oswald, Digital Design Director, Wireless Multimedia Division, STMicroelectronics [read more]