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[ Post-silicon | Brochures ]
The JTAG eVC is a complete DFT verification environment capable of verifying IEEE 1149.1 test infrastructures.
[ Post-silicon | Brochures ]
The IEEE 1500 eVC is an DFT verification environment capable of verifying IEEE 1500 compliant test infrastructures.
[ Peripherals | Brochures ]
The IrDA eVC is an interface-level verification environment which can be used to verify infrared SIR, MIR and FIR interfaces.
[ Peripherals | Brochures ]
The UART eVC is an interface-level eVC which can be used to verify any UART interface.
[ Post-silicon | Papers ]
Presented at the 3rd IEEE Workshop on Infrastructure IP, Palm Spings, California, USA, this paper discusses a comprehensive approach to designing a DFT verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy.

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Functional Verification IP
UART eVC
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IrDA® eVC
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