The IEEE 1149.7 verification IP (VIP) verifies design blocks conforming to any of the six compliance levels defined by the IEEE standard, significantly reducing time to functional closure and increasing quality of first silicon. As illustrated in the diagram above, the VIP architecture is compliant to the Cadence Incisive Plan-to-Closure Methodology (IPCM) and includes:

• A Debug and Test System (DTS) Agent, capable for injecting traffic to the IEEE 1149.7 DUT in both standard and advanced protocols
  
• A TAP.7 Agent, used to monitor activities on the I/O interfaces and register file of the IEEE 1149.7 DUT
• A number of TAP.1 Agents, used to monitor or model one or more System Test Logic (STL) IEEE 1149.1 TAP controllers
  

The IEEE 1149.7 VIP supports 100% reuse of block-level tests in chip-level or board-level verification flows of IEEE 1149.7-enabled systems, which may include several TAP.7 controllers in series or star topologies.

Finally, this VIP includes a metric-driven compliance management suite which can be used to accurately assess the interoperability of IEEE 1149.7 IP in system topologies prior to integration.