Globetech Solutions :: Interview: Low-Power Design and Verification using CPF

Home > News > In the News
Home > Topics > VIP
Any of these categories - All of these categories

Interview: Low-Power Design and Verification using CPF cdnusers.org
For the full article, please visit the cdnusers.org website.

Posted on Thu, 13 September 2007 11:27:57

Functional Verification IP

	IEEE 1149.7™ VIP
	IEEE 1149.1 (JTAG) eVC
	IEEE 1500 (SECT) eVC

Functional Verification IP

	UART eVC
	CE-ATA eVC
	IrDA® eVC

Latest News

	2010-02-19 Q&A: Why The e Verification Language Is Alive And Well - Cadence.com
	2010-02-11 IPextreme and Globetech Solutions Announce Availability of Industry’s First Complete IEEE 1149.7 cJTAG IP Solution
	2009-07-15 TLM-Driven Design and Verification Solution - Cadence.com
	2008-09-05 'Compact JTAG’ standard targets on-chip debug - SCDsource

Customer Quotes

Globetech VIP major contributor for STMicro
“Globetech’s high quality products, outstanding support and on-time deliverables have made a major contribution to the success of our [CJTAG] IP development.”

François Oswald, Digital Design Director, Wireless Multimedia Division, STMicroelectronics [read more]