IEEE Ratifies First Open 'e' Language Standard for Verifying Complex System-on-Chip Designs

	2010-02-19 Q&A: Why The e Verification Language Is Alive And Well - Cadence.com
	2010-02-11 IPextreme and Globetech Solutions Announce Availability of Industry’s First Complete IEEE 1149.7 cJTAG IP Solution
	2009-07-15 TLM-Driven Design and Verification Solution - Cadence.com
	2008-09-05 'Compact JTAG’ standard targets on-chip debug - SCDsource

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"Globetech is a [Cadence] premier Verification Alliance Partner with years of verification expertise, complemented by readily available verification IP. They substantially improve customers' time to productivity, and give them greater confidence in first-pass success."

Steven Glaser, Corporate VP Marketing, Cadence Verification Division [read more]